Câu 1:

//cau1

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity shift is port (

s: in std_logic_vector(2 downto 0);

input: in std_logic_vector(7 downto 0);

output: out std_logic_vector(7 downto 0);

end shift;

architecture behavior of shift is

   process(s,input)

  case s is

  when "000" => output <= input;

  when "001" => output <= input(7) & input(6 downto 0);

  when "010" => output <= '1' & input(7 downto 1);

  when "100" => output <= input(6 downto 0) & '0';

  when "101" => output <= input;

  when "110" => output <= input(0) & input(7 downto 1);

  when "111" => output <= '0' & input(7 downto 1);

   end process;

end behavior;

------------------------------------------------------

Câu 2:

//cau2

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cau2 is port (

s: in std_logic_vector(2 downto 0);

a,b : in std_logic_vector(3 downto 0);

f: out std_logic_vector(3 downto 0));

end cau2;

architecture Behavior is cau2 is

process(s,a,b)

case s is

when "000" => f <= a + b;

when "001" => f <= a + 1;

when "010" => f <= b + 1;

when "011" => f <= a;

when "100" => f <= a - b;

when "101" => f <= a xor b;

when "110" => f <= a and b;

end case;

end process;

end Behavior;

-------------------------------------------------

Câu 3:

//cau3

library ieee;

use ieee.std_logic_1164.all;

entity bcd_adder is port(

      bcd1: in std_logic_vector(3 downto 0);

      bcd2: in std_logic_vector(3 downto 0);

      bcdcin: in std_logic;

      bcdsum: out std_logic_vector(3 downto 0);

      bcdcout: out std_logic);

end bcd_adder;

architecture behavior of bcd_adder is

component adder_4bit is port(

      a: in std_logic_vector(3 downto 0);

      b: in std_logic_vector(3 downto 0);

      ci: in std_logic;

      sum: out std_logic_vector(3 downto 0);

      cout: out std_logic);

    end component;

signal c1,c2: std_logic;

signal s,x: std_logic_vector(3 downto 0);

  u1: adder_4bit port map(a(3) => bcd1(3),a(2) => bcd1(2),a(1) => bcd1(1), a(0) => bcd1(0),

b(3) => bcd2(3),b(2) => bcd2(2), b(1) => bcd2(1), b(0) => bcd2(0),

ci => bcdin,sum(3) => s(3), sum(2) => s(2), sum(1) => s(1),sum(0) => s(0),

cout => c1);

c2 <= ((s(3)and s(2))or(s(3)and s(1))or(c1);

x <= "0110" when c2 = '1' else x<= "0000";

  u2: adder_4bit port map(a(3) => s(3),a(2) => s(2),a(1) => s(1), a(0) => s(0),

b(3) => x(3),b(2) => x(2), b(1) => x(1), b(0) => x(0),

ci => '0',sum(3) => bcdsum(3), sum(2) => bcdsum(2), sum(1) => bcdsum(1),sum(0) => bcdsum(0),

cout => bcdcout);

end behavior;

----------------------------------------

Câu 4 a:

//Cau4

library ieee;

use ieee.std_logic_1164.all;

entity cau4 is port(

clk,rst_n,c : in std_logic;

a,b : out std_logic);

end cau4;

architecture behavior of cau4 is

    type state is std_logic_vector(1 downto 0);

    constant S0: state:= "00";

    constant S1: state:= "01";

    constant S2: state:= "10";

    constant S3: state:= "11";

    signal pr_state, nx_state: state;

    process(clk,rst_n)

if rst_n = '1' then pr_state <= rst_n state;

elseif (clk event and clk = '1') then pr_state <= nx_state;

    end if;

    end process;

    process(c,pr_state)

    case pr_state is

when S0 =>

 if c = '0' then a = '1' & b = '0';

nx_state <= S1;

 else a = '0' & b = '1';

nx_state <= S3;

 end if;

when S1 =>

                  if c = '0' then a = '0' & b = '0';

 nx_state <= S2;

 else a = '0' & b = '0';

nx_state <= S0;

 end if;

when S2 =>

     if c = '0' then a = '0' & b = '0';

nx_state <= S0;

 else a = '1' & b = '0';

nx_state <= S1;

 endif;

when S3 => a = '0' & b = '0';

nx_state <= S0;

end case;

    end process;

end behavior;

----------------------------------

Câu 4 b:

//Cau4b

library ieee;

use ieee.std_logic_1164.all;

entity cau4 is port(

clk,rst_n,a,b : in std_logic;

x,y : out std_logic);

end cau4;

architecture behavior of cau4 is

    type state is std_logic_vector(1 downto 0);

    constant S0: state:= "00";

    constant S1: state:= "01";

    constant S2: state:= "10";

    constant S3: state:= "11";

    signal pr_state, nx_state: state;

    process(clk,rst_n)

if rst_n = '1' then pr_state <= rst_n state;

elseif (clk event and clk = '1') then pr_state <= nx_state;

    end if;

    end process;

    process(a,b,pr_state)

    case pr_state is

when S0 =>

 if a = '0' then x = '0' & y = '0';

nx_state <= S1;

 else x = '1' & y = '1';

nx_state <= S0;

 end if;

when S1 =>

                  if a = '0' & b = '0' then x = '1' & y = '1';

 nx_state <= S0;

 elseif a = '0' & b = '1' then x = '1' & y = '1';

nx_state <= S2;

 elseif a = '1' & b = '0' then x = '0' & y = '0';

nx_state <= S1;

 elseif a = '1' & b = '1' then x = '1' & y = '1';

nx_state <= S3;

 end if;

when S2 =>

     if a = '0' then x = '0' & y = '0';

 nx_state <= S1;

 elseif x = '1' & y = '1';

nx_state <= S2;

 endif;

when S3 => 

 if a = '0' then x = '1' & y = '1';

 nx_state <= S0;

 elseif x = '1' & y = '1';

nx_state <= S3;

 end if;

end case;

    end process;

end behavior;

----------------------------------

Câu 5:

//cau5

library ieee;

use ieee.std_logic_1164.all;

entity cau5 is port(

clk,rst_n,start : in std_logic;

m,n : out std_logic);

end cau4;

architecture behavior of cau5 is

    type state is std_logic_vector(2 downto 0);

    constant S0: state:= "000";

    constant S1: state:= "001";

    constant S2: state:= "010";

    constant S3: state:= "011";

    constant S4: state:= "100";

    constant S5: state:= "101";

    constant S6: state:= "110";

    constant S7: state:= "111";

    signal pr_state, nx_state: state;

    process(clk,rst_n)

if rst_n = '1' then pr_state <= rst_n state;

elseif (clk event and clk = '1') then pr_state <= nx_state;

    end if;

    end process;

  process(start,pr_state)

    case pr_state is

when S0 =>

 if start = '0' then m = '0' & n = '0';

nx_state <= S7;

 else m = '0' & n = '0';

nx_state <= S6;

 end if;

when S1 =>

                  if start = '0' or start = '1' then m = '0' & n = '0';

 nx_state <= S6;

 end if;

when S2 =>

     if start = '0' or start = '1' then m = '1' & n = '0';

nx_state <= S3;

 endif;

when S3 => 

 if start = '0' or start = '1' then m = '0' & n = '0';

nx_state <= S4;

 end if;

when S4 =>

 if start = '0' then m = '0' and n = '0';

nx_state <= S7;

 else m = '0' and n = '0';

nx_state <= s4;

 end if;

when S5 =>

 if start = '0' then m = '0' and n = '0';

  nx_state <= S4;

 else  m = '0' and n = '0';

 nx_state <= s5;

 end if;

when s6 =>

 if start = '0' or start = '1' then m = '0' and n = '0';

nx_state <= S0;

 end if;

when s7 =>

 if start = '1' then m = '0' and n = '1';

nx_state <= s1;

 else m = '0' and n = '0';

nx_state <= s0;

 end if;

end case;

    end process;

end behavior;

--------------------------------

Câu 6 a:

//cau6a

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity traffic_light is port (

clk,reset: in std_logic;

R,Y,G : out std_logic);

end traffic_light;

architecture behavior of traffic_light is

type state_type is (s0,s1,s2);

signal state: state_type;

signal count: std_logic_vector(3 downto 0);

constant sec8S: std_logic_vector(3 downto 0) := "1000";

constant sec4S: std_logic_vector(3 downto 0) := "0100";

constant sec12S: std_logic_vector(3 downto 0) := "1100";

    process(clk,reset)

if(!reset) then state <= s0;

count <= "0000";

elseif clk'event and clk = '1' then

  case state is

when s0 =>

 if count < sec8s then state <= s0;

count <= count + 1;

  else

state <= s1;

count <= "0000";

when s1 =>

  if count < sec4s then state <= s1;

count <= count + 1;

  else state <= s2;

count <= "0000";

when s2 =>

  if count < sec12s then state <= s2;

 count <= count + 1;

  else state <= s0;

count <= "0000";

when other => state <= s0;

  endcase;

end if;

    end process;

G <= s0;Y <= s1; R <= s2;

end behavior;

----------------------------------

Câu 6 b:

//cau6b

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity traffic_light is port (

clk,reset,stop: in std_logic;

G,Y,R : out std_logic);

end traffic_light;

architecture behavior of traffic_light is

type state_type is (s0,s1,s2);

signal state: state_type;

signal count: std_logic_vector(3 downto 0);

constant sec12S: std_logic_vector(3 downto 0) := "1000";

constant sec3S: std_logic_vector(3 downto 0) := "0100";

constant sec15S: std_logic_vector(3 downto 0) := "1100";

G <= s0; Y <= s1; R <= s2;

    process(clk,reset,stop)

if(!reset) then state <= s0;

count <= "0000";

elseif clk'event and clk = '1' then

  if stop'event and stop = '1' then state <= s2;

  else

  case state is

when s0 =>

 if count < sec12s then state <= s0;

count <= count + 1;

  else

state <= s1;

count <= "0000";

when s1 =>

  if count < sec3s then state <= s1;

count <= count + 1;

  else state <= s2;

count <= "0000";

when s2 =>

  if count < sec15s then state <= s2;

 count <= count + 1;

  else state <= s0;

count <= "0000";

when other => state <= s0;

  endcase;

  end if;

end if;

    end process;

end behavior;

----------------------------------

Câu 6 c:

/Cau6c

library ieee;

use ieee.std_logic_1164.all;

entity counter_down_up is port (

s,clk,reset: in std_logic;

led : out std_logic_vector(6 downto 0));

end counter_down_up;

architecture behavior of counter_down_up is

     signal digit: std_logic_vector(3 downto 0);

    process(clk,reset,s)

if reset = '1' then digit <= "0000";

elseif (clk event and clk = '1') then 

if (digit = "1001") and (s = '1') then digit <= "0000";

     else digit <= digit + "0001";

end if;

if (digit = "0000") and (s = '0') then digit <= "1001";

     else digit <= not(digit) + "0001";

end if;

end if;

    end process;

    process(digit)

case digit is

when "0000" => led <= "1000000";

when "0001" => led <= "1111001";

when "0010" => led <= "0100100";

when "0011" => led <= "0110000";

when "0100" => led <= "0011001";

when "0101" => led <= "0010010";

when "0110" => led <= "0000010";

when "0111" => led <= "1111000";

when "1000" => led <= "0000000";

when "1001" => led <= "0010000";

end case;

    end process;

end behavior;

-------------------------------

Câu 7:

//cau7

library ieee;

use ieee.std_logic_1164.all;

entity counter_down_up is port (

clk,reset: in std_logic;

led1, led2 : out std_logic_vector(6 downto 0));

end counter_down_up;

architecture behavior of counter_down_up is

     signal digit1, digit2: std_logic_vector(3 downto 0);

    process(clk,reset)

if reset = '1' then digit1 <= "0000" and digit2 <= "0000";

elseif (clk event and clk = '0') then 

if (digit1 = "1001") then digit1 <= "0000" and digit2 <= digit2 + "0001";

else digit1 <= digit1 + "0001";

end if;

if (digit2 = "0001") and (digit1 = "0010") then digit1 <= "0000" and digit2 <= "0000";

end if;

end if;

    end process;

    process(digit)

case digit is

when "0000" => led <= "1000000";

when "0001" => led <= "1111001";

when "0010" => led <= "0100100";

when "0011" => led <= "0110000";

when "0100" => led <= "0011001";

when "0101" => led <= "0010010";

when "0110" => led <= "0000010";

when "0111" => led <= "1111000";

when "1000" => led <= "0000000";

when "1001" => led <= "0010000";

end case;

    end process;

end behavior;

-------------------------------

Câu 9:

//cau9

library ieee;

use ieee.std_logic_1164.all;

entity counter_up is port (

clk,reset: in std_logic;

led1, led2 : out std_logic_vector(6 downto 0));

end counter_up;

architecture behavior of counter_up is

     signal digit1, digit2: std_logic_vector(3 downto 0);

    process(clk,reset)

if reset = '1' then digit1 <= "0000" and digit2 <= "0000";

elseif (clk event and clk = '0') then 

if (digit1 = "1001") then digit1 <= "0000" and digit2 <= digit2 + "0001";

else digit1 <= digit1 + "0001";

end if;

if (digit2 = "0010") and (digit1 = "0100") then digit1 <= "0000" and digit2 <= "0000";

end if;

end if;

    end process;

    process(digit)

case digit is

when "0000" => led <= "1000000";

when "0001" => led <= "1111001";

when "0010" => led <= "0100100";

when "0011" => led <= "0110000";

when "0100" => led <= "0011001";

when "0101" => led <= "0010010";

when "0110" => led <= "0000010";

when "0111" => led <= "1111000";

when "1000" => led <= "0000000";

when "1001" => led <= "0010000";

end case;

    end process;

end behavior;