VHDL
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06-20-2011, 02:52 PM
1. Thiết kế và mô phỏng Flip-Flop RSFF đồng bộ tín hiệu reset
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFF is
d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC
end DFF;
architecture DFF of DFF is
process(clk,rst)
if(clk'event and clk='1') then
if(rst='1') then
q<='0';
else
q<=d;
end if;
end if;
end process;
end DFF;
4. Thiết kế và mô phỏng Flip-Flop JKFF không đồng bộ tín hiệu reset
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity JKFF is
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC
end JKFF;
architecture JKFF of JKFF is
signal q0: std_logic;
process(clk,rst,j,k)
variable jk: std_logic_vector (1 downto 0);
if(rst='1') then
q0<='0';
else if(clk'event and clk='1') then
jk:=j&k;
case jk is
when "00" =>q0<=q0;
when "01" =>q0<='0';
when "10" =>q0<='1';
when others =>q0<=not(q0);
end case;
end if;
end if;
end process;
q<=q0;
end JKFF;
6. Thiết kế và mô phỏng Flip-Flop RSFF không đồng bộ tín hiệu reset
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSFF is
r : in STD_LOGIC;
s : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC
end RSFF;
architecture RSFF of RSFF is
signal q0: std_logic;
process (clk,rst,r,s)
variable rs:std_logic_vector (1 downto 0);
rs:=r&s;
if (rst='1') then
q0<='0';
else if (clk'event and clk='1') then
case rs is
when "00"=>q0<=q0;
when "01"=>q0<='1';
when "10"=>q0<='0';
when others=>q0<='X';
end case;
end if;
end if;
end process;
q<=q0;
end RSFF;
7. Mạch 3 đầu vào, 2 trong 3 đầu vào bằng 1 thì đầu ra bằng 1
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity \3dauvao\ is
sel: in std_logic_vector (2 downto 0);
q: out STD_LOGIC
end \3dauvao\;
architecture \3dauvao\ of \3dauvao\ is
with sel select
q<='1' when "011",
'1' when "110",
'1' when "101",
'X' when others;
end \3dauvao\;
8. Mạch 3 trạng thái
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mach3trangthai is
input : in STD_LOGIC;
ena : in STD_LOGIC;
output : out STD_LOGIC
end mach3trangthai;
architecture mach3trangthai of mach3trangthai is
output<=input when ena='0' else
'Z';
end mach3trangthai;
9. IC 74139 lệnh song song
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity IC74139 is
sel : in STD_LOGIC_VECTOR(2 downto 0);
output : out STD_LOGIC_VECTOR(3 downto 0)
end IC74139;
architecture IC74139 of IC74139 is
with sel select
output<="1110" when "000",
"1101" when "001",
"1011" when "010",
"0111" when "011",
"1111" when others;
end IC74139;
10. IC 74139 lệnh nối tiếp
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity IC74139 is
sel : in STD_LOGIC_VECTOR(2 downto 0);
output : out STD_LOGIC_VECTOR(3 downto 0)
end IC74139;
architecture IC74139 of IC74139 is
process (sel)
case sel is
when "000"=>output<="1110";
when "001"=>output<="1101";
when "010"=>output<="1011";
when "011"=>output<="0111";
when others=>output<="1111";
end case;
end process;
end IC74139;
11. IC 74138 lệnh song song
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity IC74138 is
sel : in STD_LOGIC_VECTOR(5 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0)
end IC74138;
architecture IC74138 of IC74138 is
with sel select
output<="11111110" when "001000",
"11111101" when "001001",
"11111011" when "001010",
"11110111" when "001011",
"11101111" when "001100",
"11011111" when "001101",
"10111111" when "001110",
"01111111" when "001111",
"11111111" when others;
end IC74138;
12. IC 74138 lệnh nối tiếp
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ic74138nt is
sel : in STD_LOGIC_VECTOR(5 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0)
end ic74138nt;
architecture ic74138nt of ic74138nt is
process(sel)
case sel is
when "001000"=>output<="11111110";
when "001001"=>output<="11111101";
when "001010"=>output<="11111011";
when "001011"=>output<="11110111";
when "001100"=>output<="11101111";
when "001101"=>output<="11011111";
when "001110"=>output<="10111111";
when "001111"=>output<="01111111";
when others =>output<="11111111";
end case;
end process;
end ic74138nt;
13. Đếm tiến với Kd bất kỳ
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demtien is
generic(n:integer:=10);
clk : in STD_LOGIC;
q : out integer range 0 to n-1
end demtien;
architecture demtien of demtien is
process(clk)
variable temp: integer range 0 to n;
if(clk'event and clk='1') then
temp:=temp+1;
if(temp=10) then
temp:=0;
end if;
end if;
q<=temp;
end process;
end demtien;
14. Đếm lùi với Kd bất kỳ
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demlui is
generic (n:integer:=10);
clk : in STD_LOGIC;
output : out integer range 0 to n-1
end demlui;
architecture demlui of demlui is
process(clk)
variable temp: integer range n downto -1;
if(clk'event and clk='1') then
temp:=temp-1;
if(temp=-1) then
temp:=n-1;
end if;
end if;
output<=temp;
end process;
end demlui;
15. MUX 4-1
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux41 is
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(1 downto 0);
y : out STD_LOGIC
end mux41;
architecture mux41 of mux41 is
process(sel)
case sel is
when "00"=>y<=a;
when "01"=>y<=b;
when "10"=>y<=c;
when others=>y<=d;
end case;
end process;
end mux41;
18. DEMUX 1-8
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demux18 is
x : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
end demux18;
architecture demux18 of demux18 is
with sel select
y<="ZZZZZZZ"&x when "000",
"ZZZZZZ"&x&'Z' when "001",
"ZZZZZ"&x&"ZZ" when "010",
"ZZZZ"&x&"ZZZ" when "011",
"ZZZ"&x&"ZZZZ" when "100",
"ZZ"&x&"ZZZZZ" when "101",
'Z'&x&"ZZZZZZ" when "110",
x&"ZZZZZZZ" when "111",
unaffected when others;
end demux18;
19. Bộ so sánh 4 bít
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sosanh4bit is
generic (n:integer:=4);
a,b : in std_logic_vector (n-1 downto 0);
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC
end sosanh4bit;
architecture sosanh4bit of sosanh4bit is
y1<='1' when a>b else '0';
y2<='1' when a=b else '0';
y3<='1' when a<b else '0';
end sosanh4bit;
20.Bộ ghi dịch 4 bít
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ghidich4bit is
generic (n:integer:=4);
d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(n-1 downto 0)
end ghidich4bit;
architecture ghidich4bit of ghidich4bit is
signal temp:std_logic_vector (n-1 downto 0);
process(clk,rst,d)
if (rst='1') then
temp<=(others=>'0');
elsif(clk'event and clk='1') then
temp<=temp((n-2) downto 0)&d;
end if;
output<=temp;
end process;
end ghidich4bit;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
21. Bộ cộng n bít
entity bocongnbit is
generic (n:integer:=4);
a : in STD_LOGIC_vector (n-1 downto 0);
b : in STD_LOGIC_vector (n-1 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_vector (n-1 downto 0);
cout : out STD_LOGIC
end bocongnbit;
architecture bocongnbit of bocongnbit is
process(a,b,cin)
variable c: std_logic_vector (n downto 0);
c(0):=cin;
for i in 0 to n-1 loop
s(i)<=a(i) xor b(i) xor c(i);
c(i+1):=(a(i) and b(i)) or (a(i) and c(i)) or (b(i) and c(i));
end loop;
cout<=c(n);
end process;
end bocongnbit;
22. BCD sang LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity bcdsangled7thanh is
input : in STD_LOGIC_VECTOR(3 downto 0);
output : out std_logic_vector (6 downto 0)
end bcdsangled7thanh;
architecture bcdsangled7thanh of bcdsangled7thanh is
with input select
output<="1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1111011" when "1001",
(others=>'0') when others;
end bcdsangled7thanh;
23. BCD sang thập phân
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity bcdsangthapphan is
input : in STD_LOGIC_VECTOR(3 downto 0);
output : out integer range 0 to 15
end bcdsangthapphan;
architecture bcdsangthapphan of bcdsangthapphan is
process(input)
case input is
when "0000"=>output<=0;
when "0001"=>output<=1;
when "0010"=>output<=2;
when "0011"=>output<=3;
when "0100"=>output<=4;
when "0101"=>output<=5;
when "0110"=>output<=6;
when "0111"=>output<=7;
when "1000"=>output<=8;
when "1001"=>output<=9;
when "1010"=>output<=10;
when "1011"=>output<=11;
when "1100"=>output<=12;
when "1101"=>output<=13;
when "1110"=>output<=14;
when others=>output<=15;
end case;
end process;
end bcdsangthapphan;
24. Hexa sang Led 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity hexasangled is
input : in integer range 0 to 15;
output : out STD_LOGIC_VECTOR(6 downto 0)
end hexasangled;
architecture hexasangled of hexasangled is
with input select
output<="1111110" when 1,
"1101110" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"1111101" when 10,
"0011111" when 11,
"1001110" when 12,
"0111101" when 13,
"1001111" when 14,
"1000111" when 15,
"0000000" when others;
end hexasangled;
25. Kiểm tra tính chẵn lẻ của chuỗi n bít
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity chanlenbit is
generic (n:integer:=4);
input : in STD_LOGIC_vector (n-1 downto 0);
output : out std_logic
end chanlenbit;
architecture chanlenbit of chanlenbit is
process(input)
variable temp: std_logic;
temp:='0';
for i in input'range loop
temp:=temp xor
input(i);
end loop;
output<=temp;
end process;
end chanlenbit;
26. Bộ ALU 8 bít với 2 đầu vào 8 bít và tín hiệu điều khiển có chức năng như sau:
a. Thực hiện phép cộng khi đầu vào điều khiển nhận giá trị “00”
b. Thực hiện phép trừ khi đầu vào điều khiển nhận giá trị “01”
c. Thực hiện cổng AND khi đầu vào điều khiển nhận giá trị “10”
d. Thực hiện cổng OR khi đầu vào điều khiển nhận giá trị “11”
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
q : out STD_LOGIC_VECTOR(7 downto 0)
end alu;
architecture alu of alu is
with sel select
q <= a+b when "00",
a-b when "01",
a and b when "10",
a or b when others;
end alu;
27. Đếm số 1 trong chuỗi đầu vào 8 bít
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demso1 is
generic (n:integer:=8);
input : in STD_LOGIC_vector(n-1 downto 0);
output : out integer range 0 to n
end demso1;
architecture demso1 of demso1 is
process(input)
variable temp: integer range 0 to 8;
temp:=0;
for i in input'range loop
case input(i) is
when '1'=>temp:=temp+1;
when others=>null;
end case;
end loop;
output<=temp;
end process;
end demso1;
28. Đếm số 0 trong chuỗi đầu vào 8 bít
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demso0 is
generic (n:integer:=8);
input : in STD_LOGIC_vector(n-1 downto 0);
output : out integer range 0 to n
end demso0;
architecture demso0 of demso0 is
process(input)
variable temp: integer range 0 to 8;
temp:=0;
for i in input'range loop
case input(i) is
when '0'=>temp:=temp+1;
when others=>null;
end case;
end loop;
output<=temp;
end process;
end demso0;
29. Bộ chia tần số với hệ số bất kỳ
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity chiatan is
generic (n:integer:=6);
clk : in STD_LOGIC;
output : buffer BIT
end chiatan;
architecture chiatan of chiatan is
process(clk)
variable dem: integer range 0 to n;
if(clk'event and clk='1') then
dem:=dem+1;
if (dem=n) then
output<=not output;
dem:=0;
end if;
end if;
end process;
end chiatan;
30. Mã hóa 3-8
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mahoa38 is
input : in STD_LOGIC_VECTOR(2 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0)
end mahoa38;
architecture mahoa38 of mahoa38 is
with input select
output<="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
unaffected when others;
end mahoa38;
31. Giải mã 8-3
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity giaima83 is
input : in STD_LOGIC_VECTOR(7 downto 0);
output : out STD_LOGIC_VECTOR(2 downto 0)
end giaima83;
architecture giaima83 of giaima83 is
process(input)
case input is
when "00000001"=>output<="000";
when "00000010"=>output<="001";
when "00000100"=>output<="010";
when "00001000"=>output<="011";
when "00010000"=>output<="100";
when "00100000"=>output<="101";
when "01000000"=>output<="110";
when "10000000"=>output<="111";
when others=>null;
end case;
end process;
end giaima83;
32. Tìm mã bù 2 của 1 số
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
entity timmabu2 is
generic (n:integer:=4);
din : in STD_LOGIC_vector (n downto 0);
dout : out STD_LOGIC_vector (n downto 0)
end timmabu2;
architecture timmabu2 of timmabu2 is
process(din)
variable temp:std_logic_vector (n downto 0);
temp:=not(din);
temp:=temp+1;
dout<=temp;
end process;
end timmabu2;
Đây là bài t làm
Còn 1 số điểm t chưa hiểu
Ai có thể giảng cho t bài 21 được không ? ( bài này t xem trong sách nhưng k hiểu ):-"
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