module test (CLOCK_50, LEDG);

input CLOCK_50;

output reg [7:0] LEDG;

reg [25:0] t;

reg flag;

always @(posedge CLOCK_50)

t<=t+1;

always @(posedge t[24])

if(LEDG==8'h00)

LEDG<=8'h80;

else

case (flag)

0: begin flag<=(LEDG==8'hfe)?1:0; LEDG<={1'b1, LEDG[7:1]}; end

1: begin flag<=(LEDG==8'h80)?0:1; LEDG<={LEDG[6:0], 1'b0}; end

default LEDG<=0;

endcase

endmodule