module th(CLOCK_50, HEX2, HEX1, HEX0);

input CLOCK_50;

output reg [0:6] HEX2,HEX1,HEX0;

reg [30:0]t;

always @(posedge CLOCK_50)

t <= t + 1;

always @(posedge t[24])

if({HEX2,HEX1,HEX0} == 0)

{HEX2,HEX1,HEX0} <= {7'b100_1000, 7'b100_1111, 7'b111_1111};

else

{HEX2,HEX1,HEX0} <= {HEX0,HEX2,HEX1};

endmodule