module test (SW, CLOCK_50, LEDR);

input [1:0]SW;

input [0:0]CLOCK_50;

output [0:0]LEDR;

reg [0:0]LEDR;

reg clk;

reg [30:0]t;

always @(posedge CLOCK_50)

t<=t+1;

always @(SW)

case (SW)

0: clk<=t[24];

1: clk<=t[23];

2: clk<=t[22];

3: clk<=t[21];

default: clk<=t[24];

endcase

always @(posedge clk)

LEDR[0]=LEDR[0]^1;

endmodule