module test (CLOCK_50, SW, HEX0);

input CLOCK_50;

input [0:0]SW; //chi dùng sw0

output [0:6]HEX0; //dùng led 7doan

reg [25:0]t; //reg là bien tam mà giá tri se thay doi trong câu lenh always,có 26bit

reg [3:0]count; //count là bien dem,4bit

wire sl=SW[0]; //wire là thay doi ten bien

wire clk=t[24];

//chia tan so

always @(posedge CLOCK_50) //luôn thuc hien khi lenh bên trong khi có canh len cua xung, posedge:canh lên

t=t+1;

//main

decoderBCD disHEX (count, HEX0);

always @(posedge clk)

begin

if(sl)

begin

if(count==9)

count<=0;

else count<=count+1;

end

else

begin

if(count==0)

count<=9;

else count<=count-1;

end

end

endmodule

//display

module decoderBCD (in, out);

input [3:0]in;

output [0:6]out;

reg [0:6]out;

always @(in)

case (in)

0: out<=7'b0000_001;

1: out<=7'b1001_111;

2: out<=7'b0010_010;

3: out<=7'b0000_110;

4: out<=7'b1001_100;

5: out<=7'b0100_100;

6: out<=7'b0100_000;

7: out<=7'b0001_111;

8: out<=7'b0000_000;

9: out<=7'b0000_100;

default: out<=7'b1111_111;

endcase

endmodule