4.2 MEMORY DEVICES

In this section,we introduce the basic types of memory components that are com-

monly used in embedded systems. Now that we understand the operation of the

bus,we are able to understand the pinouts of these memories and how values are

read and written.We also need to understand the varieties of memory cells that are

used to build memories.There are several varieties of both read-only and read/write

memories,each with its own advantages.After discussing some basic characteristics

of memories,we describe RAMs and then ROMs.

4.2.1 Memory Device Organization

The most basic way to characterize a memory is by its capacity, such as 256 MB.

However,manufacturers usually make several versions of a memory of a given size,

each with a different data width. For example, a 256-MB memory may be available

in two versions:

■ Asa64M x 4-bit array,a single memory access obtains an 8-bit data item,with

a maximum of 226 different addresses.

■ Asa32M x 8-bit array, a single memory access obtains a 1-bit data item,with

a maximum of 223 different addresses.

The height/width ratio of a memory is known as its aspect ratio. The best

aspect ratio depends on the amount of memory required.

Internally, the data are stored in a two-dimensional array of memory cells as

shown in Figure 4.15. Because the array is stored in two dimensions,the n-bit address

received by the chip is split into a row and a column address (with n = r+ c).

The row and column select a particular memory cell. If the memory’s external

width is 1 bit, the column address selects a single bit; for wider data widths, the

column address can be used to select a subset of the columns. Most memories

include an enable signal that controls the tri-stating of data onto the memory’s

pins.We will see in Section 4.4.1 how the enable pin can be used to easily build

large memories from multiple banks of memory chips. A read/write signal (R/W in

the gure) on read/write memories controls the direction of data transfer;memory

chips do not typically have separate read and write data pins.

4.2.2 Random-Access Memories

Random-access memories can be both read and written. They are called random

access because, unlike magnetic disks, addresses can be read in any order. Most

bulk memory in modern systems is dynamic RAM (DRAM). DRAM is very dense;

it does, however, require that its values be refreshed periodically since the values

inside the memory cells decay over time.

The dominant form of dynamic RAM today is the synchronous DRAMs

(SDRAMs), which uses clocks to improve DRAM performance. SDRAMs use

Row Address Select (RAS) and Column Address Select (CAS) signals to break the

address into two parts,which select the proper row and column in the RAM array.

Signal transitions are relative to the SDRAM clock,which allows the internal SDRAM

operations to be pipelined.

As shown in Figure 4.16, transitions on the control signals are related to a clock

[Mic00]. RAS and CAS can therefore become valid at the same time. The address

lines are not shown in full detail here; some address lines may not be active depend-

ing on the mode in use. SDRAMs use a separate refresh signal to control refreshing.

DRAM has to be refreshed roughly once per millisecond. Rather than refresh the

entirememory at once,DRAMs refresh part of thememory at a time.When a section

of memory is being refreshed, it cannot be accessed until the refresh is complete.

The memory refresh occurs over fairly few seconds so that each section is refreshed

every few microseconds.

SDRAMs include registers that control the mode in which the SDRAM operates.

SDRAMs support burstmodes that allowseveral sequential addresses to be accessed

by sending only one address. SDRAMs generally also support an interleaved mode

that exchanges pairs of bytes.

Even faster synchronous DRAMs,known as double-data rate (DDR) SDRAMs

or DDR2 and DDR3 SDRAMs, are now in use. The details of DDR operation are

beyond the scope of this book, but the basic capabilities of DDR memories are

similar to those of single-rate SDRAMs; DDRs simply use sophisticated circuit

techniques to perform more operations per clock cycle.

SIMMs and DIMMs

Memory for PCs is generally purchased as single in-line memory modules

(SIMMs) or double in-line memory modules (DIMMs). A SIMM or DIMM is

a small circuit board that ts into a standard memory socket. A DIMM has two sets

of leads compared to the SIMM’s one. Memory chips are soldered to the circuit

board to supply the desired memory.

4.2.3 Read-Only Memories

Read-only memories (ROMs) are preprogrammed with xed data.They are very

useful in embedded systems since a great deal of the code, and perhaps some data,

does not change over time. Read-only memories are also less sensitive to radiation-

induced errors.

There are several varieties of ROMavailable.The rst-level distinction to bemade

is between factory-programmed ROM (sometimes called mask-programmed

ROM) and eld-programmable ROM. Factory-programmed ROMs are ordered

from the factory with particular programming. ROMs can typically be ordered in

lots of a few thousand, but clearly factory programming is useful only when the

ROMs are to be installed in some quantity.

Field-programmable ROMs, on the other hand, can be programmed in the lab.

Flash memory is the dominant formof eld-programmable ROMand is electrically

erasable. Flash memory uses standard system voltage for erasing and programming,

allowing it to be reprogrammed inside a typical system.This allows applications such

as automatic distribution of upgrades—the ash memory can be reprogrammed

while downloading the new memory contents from a telephone line. Early ash

memories had to be erased in their entirety;modern devices allow memory to be

erased in blocks. Most ash memories today allow certain blocks to be protected.

A common application is to keep the boot-up code in a protected block but allow

updates to other memory blocks on the device. As a result, this form of ash is

commonly known as boot-block ash.

4.3 I/O DEVICES

In this section we survey some input and output devices commonly used in embed-

ded computing systems. Some of these devices are often found as on-chip devices

in micro-controllers; others are generally implemented separately but are still com-

monly used. Looking at a few important devices now will help us understand both

the requirements of device interfacing in this chapter and the uses of devices in

programming in this and later chapters.

4.3.1 Timers and Counters

Timers and counters are distinguished from one another largely by their use,

not their logic. Both are built from adder logic with registers to hold the current

value,with an increment input that adds one to the current register value. However,

a timer has its count connected to a periodic clock signal to measure time intervals,

while a counter has its count input connected to an aperiodic signal in order to

count the number of occurrences of some external event. Because the same logic

can be used for either purpose, the device is often called a counter/timer.

Figure 4.17 shows enough of the internals of a counter/timer to illustrate its

operation.An n-bit counter/timer uses an n-bit register to store the current state of

the count and an array of half subtractors to decrement the count when the count

signal is asserted. Combinational logic checks when the count equals zero; the done

output signals the zero count. It is often useful to be able to control the time-out,

rather than require exactly 2n events to occur. For this purpose, a reset register

provides the value with which the count register is to be loaded.The counter/timer

provides logic to load the reset register. Most counters provide both cyclic and

acyclic modes of operation. In the cyclic mode,once the counter reaches the done

state, it is automatically reloaded and the counting process continues. In acyclic

mode, the counter/timer waits for an explicit signal from the microprocessor to

resume counting.

A watchdog timer is an I/O device that is used for internal operation of a

system.As shown in Figure 4.18, the watchdog timer is connected into the CPU bus

and also to the CPU’s reset line.The CPU’s software is designed to periodically reset

the watchdog timer,before the timer ever reaches its time-out limit. If the watchdog

timer ever does reach that limit, its time-out action is to reset the processor. In that

case, the presumption is that either a software aw or hardware problemhas caused

the CPU to misbehave. Rather than diagnose the problem, the system is reset to get

it operational as quickly as possible.

4.3.2 A/D and D/A Converters

Analog/digital (A/D) and digital/analog (D/A) converters (typically known

as ADCs and DACs, respectively) are often used to interface nondigital devices to

embedded systems. The design of A/D and D/A converters themselves is beyond

the scope of this book; we concentrate instead on the interface to the micropro-

cessor bus. Because A/D conversion requires more complex circuitry, it requires a

somewhat more complex interface.

Analog/digital conversion requires sampling the analog input before convert-

ing it to digital form. A control signal causes the A/D converter to take a sample

and digitize it.

There are several different types ofA/D converter circuits, some of which take a

constant amount of time,while the conversion time of others depends on the sam-

pled value.Variable-time converters provide a done signal so that themicroprocessor

knows when the value is ready.

A typical A/D interface has, in addition to its analog inputs, two major digital

inputs. A data port allows A/D registers to be read and written, and a clock input

tells when to start the next conversion.

D/A conversion is relatively simple, so the D/A converter interface generally

includes only the data value. The input value is continuously converted to analog

form.

4.3.3 Keyboards

A keyboard is basically an array of switches, but it may include some internal logic

to help simplify the interface to the microprocessor. In this chapter,we build our

understanding from a single switch to a microprocessor-controlled keyboard.

A switch uses a mechanical contact to make or break an electrical circuit.

The major problem with mechanical switches is that they bounce as shown in

Figure 4.19.When the switch is depressed by pressing on the button attached to

the switch’s arm, the force of the depression causes the contacts to bounce several

times until they settle down. If this is not corrected, it will appear that the switch

has been pressed several times,giving false inputs.A hardware debouncing circuit

can be built using a one-shot timer. Software can also be used to debounce switch

inputs. A raw keyboard can be assembled from several switches. Each switch in a

rawkeyboard has its own pair of terminals,making rawkeyboards impracticalwhen

a large number of keys is required.

More expensive keyboards, such as those used in PCs, actually contain a

microprocessor to preprocess button inputs. PC keyboards typically use a 4-bit

microprocessor to provide the interface between the keys and the computer.

The microprocessor can provide debouncing, but it also provides other functions

as well. An encoded keyboard uses some code to represent which switch is cur-

rently being depressed. At the heart of the encoded keyboard is the scanned array

of switches shown in Figure 4.20. Unlike a raw keyboard, the scanned keyboard

array reads only one row of switches at a time.The demultiplexer at the left side of

the array selects the row to be read.When the scan input is 1, that value is trans-

mitted to one terminal of each key in the row. If the switch is depressed, the 1 is

sensed at that switch’s column. Since only one switch in the column is activated,

that value uniquely identies a key.The row address and column output can be used

for encoding, or circuitry can be used to give a different encoding.

A consequence of encoding the keyboard is that combinations of keys may not

be represented. For example, on a PC keyboard, the encoding must be chosen so

A scanned key array.

that combinations such as control-Q can be recognized and sent to the PC.Another

consequence is that rollover may not be allowed. For example, if you press “a,”and

then press “b” before releasing “a,” in most applications you want the keyboard to

send an “a” followed by a “b.” Rollover is very common in typing at even modest

rates. A naive implementation of the encoder circuitry will simply throw away any

character depressed after the rst one until all the keys are released.The keyboard

microcontroller can be programmed to provide n-key rollover, so that rollover

keys are sensed, put on a stack, and transmitted in sequence as keys are released.

4.3.4 LEDs

Light-emitting diodes (LEDs) are often used as simple displays by themselves,

and arrays of LEDs may form the basis of more complex displays. Figure 4.21 shows

how to connect an LED to a digital output. A resistor is connected between the

output pin and the LED to absorb the voltage difference between the digital output

voltage and the 0.7 V drop across the LED.When the digital output goes to 0, the

LED voltage is in the device’s off region and the LED is not on.

4.3.5 Displays

A display device may be either directly driven or driven from a frame buffer. Typi-

cally, displays with a small number of elements are driven directly by logic, while

large displays use a RAM frame buffer.

The n-digit array, shown in Figure 4.22, is a simple example of a display that is

usually directly driven. A single-digit display typically consists of seven segments;

each segment may be either an LED or a liquid crystal display (LCD) element.

This display relies on the digits being visible for some time after the drive to the

digit is removed,which is true for both LEDs and LCDs. The digit input is used to

choose which digit is currently being updated, and the selected digit activates its

display elements based on the current data value.The display’s driver is responsible

for repeatedly scanning through the digits and presenting the current value of each

to the display.

A frame buffer is a RAMthat is attached to the systembus.Themicroprocessor

writes values into the frame buffer in whatever order is desired. The pixels in the

frame buffer are generally written to the display in raster order (by tradition, the

screen is in the fourth quadrant) by reading pixels sequentially.

Many large displays are built using LCD. Each pixel in the display is formed by

a single liquid crystal. LCD displays present a very different interface to the system

because the array of pixel LCDs can be randomly accessed. Early LCD panels were

called passive matrix because they relied on a two-dimensional grid of wires to

address the pixels. Modern LCD panels use an active matrix system that puts a

transistor at each pixel to control access to the LCD.Active matrix displays provide

higher contrast and a higher-quality display.

4.3.6 Touchscreens

A touchscreen is an input device overlaid on an output device. The touchscreen

registers the position of a touch to its surface. By overlaying this on a display, the

user can react to information shown on the display.

The two most common types of touchscreens are resistive and capacitive.

A resistive touchscreen uses a two-dimensional voltmeter to sense position. As

shown in Figure 4.23, the touchscreen consists of two conductive sheets separated

by spacer balls. The top conductive sheet is exible so that it can be pressed to

touch the bottom sheet.A voltage is applied across the sheet; its resistance causes a

voltage gradient to appear across the sheet. The top sheet samples the conductive

sheet’s applied voltage at the contact point. An analog/digital converter is used to

measure the voltage and resulting position. The touchscreen alternates between

x and y position sensing by alternately applying horizontal and vertical voltage

gradients.

4.4 COMPONENT INTERFACING

Building the logic to interface a device to a bus is not too difcult but does take

some attention to detail.We rst consider interfacing memory components to the

bus, since that is relatively simple,and then use those concepts to interface to other

types of devices.

4.4.1 Memory Interfacing

If we can buy a memory of the exact size we need, then the memory structure is

simple. If we need more memory than we can buy in a single chip, then we must

construct the memory out of several chips.We may also want to build a memory

that is wider than we can buy on a single chip; for example, we cannot generally

buy a 32-bit-wide memory chip.We can easily construct a memory of a given width

(32 bits, 64 bits, etc.) by placing RAMs in parallel.

We also need logic to turn the bus signals into the appropriate memory signals.

For example,most busses won’t send address signals in row and column form.We

also need to generate the appropriate refresh signals.

4.4.2 Device Interfacing

Some I/O devices are designed to interface directly to a particular bus, forming

glueless interfaces. But glue logic is required when a device is connected to a

bus for which it is not designed.

An I/Odevice typically requires amuch smaller range of addresses than amemory,

so addresses must be decoded much more nely. Some additional logic is required

to cause the bus to read and write the device’s registers. Example 4.1 shows one

style of interface logic.